The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs and the IC is then referred to as a complementary MOS or CMOS integrated circuit (IC). There is a continuing trend to incorporate more and more circuitry on a single IC chip. To incorporate the increasing amount of circuitry, the size of each individual device in the circuit and the size and spacing between device elements (the feature size) must decrease.
High dielectric constant materials, also referred to as “high-k dielectrics,” such as hafnium dioxide (HfO2), hafnium silicate oxide nitride (HfSiON), or zirconium dioxide (ZrO2), are considered for the 45 nm node technology and beyond to allow further scaling of gate dielectrics. To prevent Fermi-level pinning, metal gates (MG) with the proper work function are used as gate electrodes on the high-k gate dielectrics. Such metal gate electrodes typically are formed of metal-comprising materials such as lanthanum (La), aluminum (Al), magnesium (Mg), titanium-based materials such as titanium nitride (TiN), tantalum-based materials such as tantalum nitride (TaN) or tantalum carbide (Ta2C), and the like. Often, a thin oxide forms on the metal-comprising material when exposed to an ambient environment. The oxide may serve as protection of the metal-comprising material from contamination.
The formation of features, such as gate dielectrics and metal gates, is performed using photolithography. Generally, during photolithography, an image is focused on a wafer to expose and pattern a layer of material, such as a hydrocarbon-based photoresist material, that is deposited on another material layer of the wafer. In turn, the photoresist material is utilized as a mask to define device features, such as gate electrodes, conductive lines, doping regions, or other structures associated with ICs in the material layer of the semiconductor wafer. After a feature is formed, the photoresist is removed from the features.
Photoresist typically is removed using a sulfuric acid/hydrogen peroxide mixture (SPM), propylene glycol methyl ether acetate (PGMEA), or a dry chemistry, such as a plasma. However, these conventional removal methods prove unsatisfactory for the removal of photoresist from metal-comprising material, such as that used to form metal gate electrodes. For example, SPM is an aqueous-based composition with a pH of about 1 and thus results in removal of not only the resist but also the metal-comprising material and any oxide formed thereon. Removal of any portion of the metal-comprising material and its oxide can result in catastrophic effects on MOSFET performance. PGMEA tends to leave residue particles on the metal-comprising material, which may result in a threshold voltage shift of the resulting MOSFET. Dry chemistries typically do not remove all of the photoresist and, thus, have to be followed by wet chemistry etches, such as with SPM or PGMEA, that in turn present the same issues set forth above.
Accordingly, it is desirable to provide a method for removing a photoresist from a metal-comprising material that does not leave residue that may undesirably affect resulting device performance. In addition, it is desirable to provide a method for removing a photoresist from a metal-comprising material that does not remove at least a portion of the metal-comprising material or the oxide formed thereon. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.